1. Field of the Invention
The present invention pertains to the polishing of wafers, and more particularly to the accurate polishing of wafers of semiconductor material, suitable for use in a semiconductor processing clean room environment.
2. Description of Related Art
The production of semiconductor devices, such as integrated circuits, begins with the preparation of high quality semiconductor wafers. Due to the purity of the material required, unprocessed semiconductor "blanks" have a substantial cost and, because of their relatively thin wafer construction and relatively fragile material composition, are susceptible to breaking caused by over-bending and chipping caused by inadvertent contact with the wafer edge. With the development of each layer on a semiconductor surface, the cost of the semiconductor wafer is substantially increased. During integrated circuit production as circuit layers are built up on the blank, an extremely flat surface is desired on at least one face of the wafer. Flatness is attained by polishing, which generally includes supporting the back side of the wafer with a wafer carrier or chuck, carried by an arm or other apparatus for pressing the front face of the wafer against a polishing surface. The polishing process typically employs one or more chemical actions as well as an abrasive, mechanical action. Accordingly, this general type of wafer production has come to be referred to as Chemical Mechanical Polishing (CMP).
Typically, the polishing surface is carried on a rigid flat table which is rotated to provide movement for the mechanical abrasion. The polishing surface is typically flooded with a special purpose material (referred to as a slurry) having the chemical and mechanical abrasion properties needed for the desired operation.
With the increasing power of electronic devices, the density of active electronic circuit components developed on a given surface area of a wafer is continually being increased. The layers of electronic circuitry developed on the face of the semiconductor wafer are typically constructed using photolithography or other techniques. In order to increase the resolution of the photo patterns which can be "printed"on the semiconductor wafer surface, the semiconductor wafer surface must be extremely flat, both in a so-called "local" sense as well as in a "global" sense. That is, typically the surface of the semiconductor wafer is divided into many local portions, each containing identical copies of the desired semiconductor device. The portion of the semiconductor's surface for any single semiconductor device is relatively small, but still must be extremely flat and free of surface irregularities, within extremely tight tolerances, oftentimes measured on a microscopic scale. Current commercial production techniques further require that the wafer front surface have a global (or edge-to-edge) planarity to facilitate batch processing of the entire usable portion of the wafer surface in a single operation. In the interest of economical manufacture, more complete utilization of the wafer surface is continually being sought, so that a larger number of electronic devices can be obtained from a single wafer, on a routine basis.
Typically, semiconductor wafers are polished many times during the course of semiconductor device fabrication. As multiple layers of conductors and dielectrics are built up on the surface of a wafer, polishing is usually required after the deposition of each layer to restore any deviation from highly demanding local and global flatness tolerances. Because so-called "out-of-flatness" tolerances must be related to the total, finished construction, it is critical that the polishing process be held to extremely close tolerances such that finished densely packed structures do not interfere with one another.
It is important, during the course of preparing the semiconductor surface, that proper amounts of polishing are applied to assure that the desired degree of flatness is attained without undesirable intrusion into the deposited layers, which might compromise their intended electronic operation. While it is possible to periodically remove the wafer being processed from the polishing apparatus in order to inspect the wafer surface, such practices are undesirable in that they subject the wafer to additional handling with an attendant risk of injury. Further, the environmental condition of the wafer must be taken into account. For example, wafers being processed are oftentimes maintained immersed in an aqueous environment. In order to facilitate remote inspection of the wafer, the wafer would have to be removed from the aqueous environment, cleaned, and dried to facilitate inspection. Care must be taken to guard against distortion of the wafer, and the introduction of wet/dry cycles may give rise to unwanted distortion and may introduce harmful contamination.
In order to overcome these drawbacks, attention has been directed to so-called in-situ end point detection. A variety of techniques have been developed over the years. For example, various electrical signals have been passed through the wafer and the area of polishing activity, with the electrical signal thereby being modified in a certain manner, dependent upon the amount of polishing of the wafer surface. In general, such techniques rely upon an indirect detection of the wafer surface characteristics. Correlation of various modifications of the electrical signal to the wafer surface characteristics typically requires considerable experience and intense research for each particular process being carried out. Changes in polishing conditions (for example changes in slurry composition, abrasive structures, polish wheel compositions and the like) oftentimes require additional study with new correlation techniques being developed in order to indirectly indicate the surface condition of the wafer being processed in an accurate manner.
The outer edges of semiconductor wafers have been monitored on a real-time basis. Wafers mounted on reciprocating arms are carried to the edge of a polishing table, and slightly beyond by the reciprocating action. Thus, for a brief instant with each cycle of reciprocation, the bottom surface of the wafer is exposed to a monitoring probe located immediately adjacent the edge of the polishing wheel. However, only a relatively minor outer portion of the wafer can be exposed in this manner if damage and/or unwanted wafer surface patterns are to be avoided. A more convenient and complete monitoring of the wafer is being sought.